1. Field of the Invention
Generally, the present invention relates to the field of manufacturing integrated circuits, and, more particularly, to the formation of so-called damascene structures in which metal trenches and vias are formed in an insulating layer, wherein the trenches and vias are formed prior to depositing the metal. Subsequently, the structure is planarized by removing the excess metal by chemical mechanical polishing.
2. Description of the Related Art
Typically, the fabrication of modern integrated circuits requires a huge number of individual process steps, wherein a typical process sequence involves the deposition of conductive, semiconductive or insulating layers on an appropriate substrate. After deposition of the corresponding layer, device features are produced by patterning the corresponding layer using well-known means, such as photolithography and etching. As a consequence, by patterning a deposited layer, a certain topography will be created that also affects deposition and patterning of subsequent layers. Since sophisticated integrated circuits require the formation of a plurality of subsequent layers, it has become standard practice to periodically planarize the surface of the substrate so as to provide for well-defined conditions for deposition and patterning of subsequent material layers. This holds true especially for so-called metallization layers in which metal interconnects are formed to electrically connect the individual device features, such as transistors, capacitors, resistors, and the like, to establish the functionality required by the circuit design.
Recently, the so-called damascene technique has become a preferred method in forming metallization layers wherein a dielectric layer is deposited and patterned to include trenches and vias that are subsequently filled with an appropriate metal, such as aluminum or copper. The excess metal is then removed, and the resulting surface is planarized by performing a chemical mechanical polishing (CMP) process. Chemical mechanical polishing has proven to be a reliable technique to remove the excess metal and planarize the resulting surface so as to leave behind metal trenches and vias that are electrically insulated from each other as required by the corresponding circuit layout. Chemical mechanical polishing typically requires the substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other by individually moving the polishing head and the polishing pad. Typically, the head and pad are rotated against each other while the relative motion is controlled to achieve as uniform a material removal as possible. During the polishing operation, a slurry that includes at least one chemically reactive agent and possibly abrasive particles is supplied to the surface of the polishing pad.
One problem involved in the chemical mechanical polishing of substrates is the very different removal rates of differing materials, such as of a metal and a dielectric material from which the excess metal has to be removed. For instance, at a polishing state where the dielectric material and the metal are simultaneously treated, i.e., after the major portion of the metal has already been removed, the removal rate for the metal exceeds the removal rate for the dielectric material. This is desirable because all metal is reliably ablated from all insulating surfaces, thereby insuring the required electrical insulation. Thus, a metal trench or via may be recessed with respect to the surrounding insulating material resulting in a trench or via that exhibits an increased electrical resistance due to the reduced cross-sectional area. In order to more clearly demonstrate a typical damascene process, reference is made to FIGS. 1a-1e. 
FIGS. 1a-1e schematically show cross-sectional views of a semiconductor structure 100 at various stages in fabricating a metallization layer according to a typical damascene process sequence.
In FIG. 1a, the semiconductor structure 100 comprises a substrate 101 bearing circuit features (not shown) and an insulating cap layer on which metal lines are to be formed. A patterned dielectric layer 102 is formed over the substrate 101 and includes openings, for example, in the form of narrow trenches 103 and wide trenches 104. The dielectric layer 102 may also comprise closely-spaced openings 109. The openings for the trenches 103, 109 and 104 are patterned in conformity with design rules to establish metal lines exhibiting the required electrical characteristics in terms of functionality and conductivity. For instance, the trench 104 is designed as a so-called wide line to provide for a low electrical resistance. The deposition of the dielectric material 102, as well as the patterning of the trenches 103, 109 and 104, is carried out by well-known deposition and photolithography techniques.
FIG. 1b schematically depicts the semiconductor structure 100 after deposition of a metal layer 105, for example, a copper layer when sophisticated integrated circuits are considered. As is evident from FIG. 1b, the topography of the metal layer 105 will be affected by the underlying pattern of the dielectric layer 102. The metal layer 105 may be deposited by chemical vapor deposition, sputter deposition or, as usually preferred with copper, by electroplating with a preceding sputter deposition of a corresponding copper seed layer. Although the precise shape of the surface profile of the metal layer 105 may depend on the deposition technique used, in principle, a surface shape will be obtained as shown in FIG. 1b. 
Subsequently, the semiconductor structure 100 will be subjected to chemical mechanical polishing, in which, as previously mentioned, the slurry and polishing pad are selected to optimally remove the excess metal in the metal layer 105. During the chemical mechanical polishing, the excess metal is removed and, finally, surface portions 120 of the dielectric material 102 will be exposed, wherein it is necessary to continue the polishing operation for a certain overpolish time to ensure clearance of the metal from all insulating surfaces in order to avoid any electrical short between adjacent metal lines. As previously mentioned, the removal rate of the dielectric material and the metal may significantly differ from each other so that upon overpolishing the semiconductor structure 100, the copper in the trenches 103, 109 and 104 will be recessed.
FIG. 1c schematically shows a typical result of chemical mechanical polishing of the structure shown in FIG. 1b. As is evident from FIG. 1c, during overpolishing the semiconductor structure 100, different materials are simultaneously polished with different removal rates. The removal rate is also dependent, to some degree, on the underlying pattern. For instance, the recessing of the metals during the overpolish time, which is also referred to as dishing, as well as the removal of the dielectric material, also referred to as erosion, is significantly affected by the type of pattern to be polished. In FIG. 1c, dishing and erosion at the wide trenches 104, as indicated by 107 and 106, respectively, are relatively moderate, whereas at the narrow lines 103, dishing 107 and erosion 106 are significantly increased. In obtaining a required electrical conductivity, circuit designers have to take into consideration a certain degree of dishing and erosion. The situation described in FIG. 1c may, however, significantly change when the deposition of the metal layer 105 is completed with an insufficient layer thickness.
In FIG. 1d, the metal layer 105 has been deposited with a thickness 110, which may not be appropriate to completely fill the wide line 104. The incomplete filling of the wide line 104 may be caused by any variations in the deposition process used.
In FIG. 1e, the semiconductor structure 100 is shown after being subjected to the chemical mechanical polishing, wherein, due to the incomplete filling of the wide line 104, a metal line is produced that lacks a significant amount of metal, as indicated by the arrow 111. The amount of dishing 111 may, in addition to the foregoing incomplete filling, be affected by the process conditions during the chemical mechanical polishing, for example, the ratio of removal rate of metal and dielectric may have changed. Thus, a variation of the deposition process and/or a variation during the chemical mechanical polishing may lead to a variation of the degree of dishing that might be outside the acceptable tolerances. Although the metal layer 105 may be deposited with a layer thickness providing a safety margin for completely filling the wide line 104, a corresponding layer thickness may, however, require a longer deposition time as well as an increased process time during polishing of the substrate, thereby resulting in a reduced throughput. Conventionally, control of the fill degree of metal lines requires the examination of cross-sections of the substrate or, for wide metal lines, the absolute thickness of the metal within these wide lines may be determined by well-established metal thickness metrology. In any case, a great deal of effort is necessary to determine the degree of metal filling within metal lines and to establish a corresponding process window for the deposition parameters and for the polishing parameters to achieve appropriately filled metal lines.
In view of the above problems, it would be highly desirable to eliminate, or at least reduce, one or more problems involved in manufacturing metal lines in a damascene structure.
Generally, the present invention is directed to a method for estimating in situ whether or not the amount of metal in a line is within specified manufacturing tolerances. To this end, an optical signal is supplied to the surface to be planarized during the chemical mechanical polishing, and the signal amplitude of the reflected light is used to verify process parameters relating to the deposition of the metal layer and/or the chemical mechanical polishing. Some CMP tools available on the market exhibit a so-called in situ endpoint detection in which a system is provided that allows one to supply a light beam on the substrate through an opening in the polishing pad surface and to detect a light beam reflected from the surface to determine the clearance of the substrate surface upon a significant change of the signal amplitude of the reflected beam. By employing such a CMP tool having an optical endpoint detection, the method of the present invention may readily be implemented in a conventional process line without adding to process complexity and costs whereby further measurements, for example, investigations of cross-sections, may be avoided or at least reduced, thereby increasing production yield.
According to one illustrative embodiment of the present invention, a method of estimating an amount of metal in a damascene structure during chemical mechanical polishing of the structure comprises directing a light beam onto a surface of the damascene structure that is being planarized. A portion of the light beam scattered by the damascene structure is then detected and a first time point is determined that is indicative of a rising edge and a second time point is determined that is indicative of a falling edge of an intensity of the portion of the scattered light beam. From a time interval defined by the first and second time points, it is then estimated that the amount of metal of the damascene structure is sufficient when a length of the time interval exceeds a predefined threshold.
According to a further illustrative embodiment of the present invention, a method of controlling an amount of metal in a recessed region of a damascene structure formed on plural substrates comprises depositing the metal over a dielectric layer, including the recessed region that is formed on a first substrate. Then, a portion of the metal is removed by chemical mechanical polishing and an optical endpoint signal obtained during the chemical mechanical polishing is detected. The method further comprises obtaining a time interval between a rising edge and a falling edge of the optical endpoint signal and controlling at least one process parameter relating to at least one of depositing the metal and the chemical mechanical polishing on the basis of-the time interval while processing a second substrate.
In a further embodiment of the present invention, a system for controlling an amount of metal in a recessed region of a damascene structure formed on a substrate comprises a CMP tool including an optical endpoint detection system. The system further comprises a control unit that is configured to determine a length of a time interval representing a substantially constant signal amplitude of an output signal supplied by the endpoint detection system.
According to yet another illustrative embodiment of the present invention, a system for estimating the amount of metal in a damascene structure comprises an optical system adapted to direct a light beam onto the surface of a substrate during chemically mechanically polishing the surface, wherein the optical system includes a detector configured to receive a light beam scattered by the surface of the substrate and to output a signal indicative of an intensity of the scattered light beam. Moreover, a control unit is provided that is configured to determine a time interval representing a period of increased substantially constant amplitude of the signal. The control unit is further configured to provide an indication signal indicating the length of the time interval.